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1 typical a pplica t ion fea t ures descrip t ion ultralow noise and spurious 0.35ghz to 6ghz integer-n synthesizer the lt c ? 6945 is a high performance, low noise, 6ghz phase- locked loop ( pll), including a reference divider, phase - frequency detector ( pfd) with phase- lock indicator, charge pump, integer feedback divider and vco output divider. the part features a buffered, programmable vco output divider with a range of 1 through 6. the differential, low noise output buffer has user-programmable output power ranging from C6 dbm to 3 dbm, and may be muted through either a digital input pin or software. the low noise reference buffer outputs a typical 0dbm square wave directly into a 50 impedance from 10 mhz to 250mhz, or may be disabled through software. the ultralow noise charge pump contains selectable high and low voltage clamps useful for vco monitoring, and also may be set to provide a v + /2 bias. all device settings are controlled through a spi- compatible serial port. ltc6945 data converter sample clock 1ghz sample clock phase noise a pplica t ions n low noise integer-n pll n 350mhz to 6ghz vco input range n C226dbc/hz normalized in-band phase noise floor n C274dbc/hz normalized in-band 1/f noise n C157dbc/hz wideband output phase noise floor n excellent spurious performance n output divider (1 to 6, 50% duty cycle) n low noise reference buffer n output buffer muting n charge pump supply from 3.15v to 5.25v n charge pump current from 250a to 11.2ma n confgurable status output n spi compatible serial port control n pllwizard? software design tool support n wireless base stations (lte, wimax, w-cdma, pcs) n broadband wireless access n microwave data links n military and secure radio n test and measurement l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and pllwizard is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. offset frequency (hz) ?160 phase noise (dbc/hz) ?150 ?130 ?110 ?100 100 10k 100k 10m 40m 6945 ta01b ?170 1k 1m ?120 ?140 ?180 dsb integration (100hz to 1ghz) rms noise = 0.014 rms jitter = 39fs f pfd = 25mhz bw = 2.3khz v vco + gnd gnd gnd gnd gnd v co + v co ? v refo + refo stat cs sclk sdi sdo v d + mute gnd rf ? gnd ltc6945 f pfd = 25mhz rf + v rf + bb ref ? ref + v ref + cp v cp + 3.3v 3.3v 3.3v 3.3v 68nh 68nh sample clock 1ghz, 7dbm 5v 3.3v 5v v tune 432 570nf 47nf 100pf 16.5 16.5 16.5 crystek cvcso-914-1000 loop bandwidth ~2.3khz 0.01f 100pf 6945 ta01b 0.1f 0.1f 0.1f spi bus 1f 1.0f 0.01f 51.1 100mhz ref 1f 100pf gnd 0.1f 100pf 100pf 50 alt sample clock 500mhz or 1ghz 3.3v 3.3v ltc6945 6945fa for more information www.linear.com/ltc6945
2 p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltages v + (v ref + , v refo + , v rf + , v vco + , v d + ) to gnd ...... 3 .6 v v cp + to gnd ......................................................... 5 .5 v voltage on cp pin ................. gn d C 0.3 v to v cp + + 0.3 v voltage on all other pins .......... gn d C 0.3 v to v + + 0.3 v operating junction temperature range , t j ( note 2) ltc 6945 i ............................................... C 40 c to 105 c junction temperature , t jmax ................................ 125 c storage temperature range .................. C 65 c to 150 c (note 1) 9 10 top view 29 gnd ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 v refo + refo stat cs sclk sdi sdo v d + v vco + gnd gnd gnd gnd gnd vco + vco ? ref ? ref + v ref + cp v cp + gnd mute gnd rf ? rf + v rf + bb 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, jcbottom = 3c/w, jctop = 26c/w exposed pad ( pin 29) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking package description junction temperature range ltc6945iufd#pbf ltc6945iufd#trpbf 6945 28-lead (4mm 5mm) plastic qfn C40c to 105c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ symbol parameter conditions min typ max units reference inputs (ref + , ref C ) f ref input frequency l 10 250 mhz v ref input signal level single-ended, 1f ac-coupling capacitors l 0.5 2 2.7 v p-p input slew rate l 20 v/s input duty cycle 50 % self-bias voltage l 1.65 1.85 2.25 v input resistance differential l 6.2 8.4 11.6 k input capacitance differential 3 pf reference output (refo) f refo output frequency l 10 250 mhz p refo output power f refo = 10mhz, r load = 50 l C0.2 3.2 dbm output impedance, disabled 800 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v ref + = v ref0 + = v d + = v rf + = v vco + = 3.3v, v cp + = 5v unless otherwise specified. all voltages are with respect to gnd. ltc6945 6945fa for more information www.linear.com/ltc6945
3 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v ref + = v ref0 + = v d + = v rf + = v vco + = 3.3v, v cp + = 5v unless otherwise specified. all voltages are with respect to gnd. symbol parameter conditions min typ max units vco input (vco + , vco C ) f vco input frequency l 350 6000 mhz p vcoi input power level r z = 50, single-ended l C8 0 6 dbm input resistance single-ended, each input l 97 121 145 rf output (rf + , rf C ) f rf output frequency l 350 6000 mhz o output divider range all integers included l 1 6 output duty cycle 50 % output resistance single-ended, each output to v rf + l 111 136 159 output common mode voltage l 2.4 v rf + v p rf(se) output power, single-ended, f rf = 900mhz rfo[1:0] = 0, r z = 50, lc match rfo[1:0] = 1, r z = 50, lc match rfo[1:0] = 2, r z = 50, lc match rfo[1:0] = 3, r z = 50, lc match l l l l C9.7 C6.8 C3.9 C1.2 C6.0 C3.6 C0.4 2.3 dbm dbm dbm dbm output power, muted r z = 50, single- ended, f rf = 900mhz, o = 2 to 6 l C60 dbm mute enable time l 110 ns mute disable time l 170 ns phase/frequency detector f pfd input frequency l 100 mhz lock indicator, available on the s tat pin and via the spi-accessible status register t lww lock window width lkwin[1:0] = 0 lkwin[1:0] = 1 lkwin[1:0] = 2 lkwin[1:0] = 3 3.0 10.0 30.0 90.0 ns ns ns ns t lwhys lock window hysteresis increase in t lww moving from locked state to unlocked state 22 % charge pump i cp output current range 12 settings (see table 5) 0.25 11.2 ma output current source/sink accuracy v cp = v cp + /2, all settings 6 % output current sour ce/sink matching i cp = 250a to 1.4ma, v cp = v cp + /2 i cp = 2ma to 11.2ma, v cp = v cp + /2 3.5 2 % % output current vs output v oltage sensitivity (note 3) l 0.1 1.0 %/v output current vs temperature v cp = v cp + /2 l 170 ppm/c output hi-z leakage current i cp = 700a, cpclo = cpchi = 0 (note 3) i cp = 11.2ma, cpclo = cpchi = 0 (note 3) 0.5 5 na na v clmp(lo) low clamp voltage cpclo = 1 0.84 v v clmp(hi) high clamp voltage cpchi = 1, referred to v cp + C0.96 v v mid mid-supply output bias ratio referred to (v cp + C gnd) 0.48 v/v reference (r) divider r divide range all integers included l 1 1023 counts ltc6945 6945fa for more information www.linear.com/ltc6945
4 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v ref + = v ref0 + = v d + = v rf + = v vco + = 3.3v, v cp + = 5v unless otherwise specified. all voltages are with respect to gnd. symbol parameter conditions min typ max units vco (n) divider n divide range all integers included l 32 65535 counts digital pin specifications v ih high level input voltage mute, cs, sdi, sclk l 1.55 v v il low level input voltage mute, cs, sdi, sclk l 0.8 v v ihys input voltage hysteresis mute, cs, sdi, sclk 250 mv input current mute, cs, sdi, sclk l 1 a i oh high level output current sdo and stat , v oh = v d + C 400mv l C2.3 C1.4 ma i ol low level output current sdo and stat , v ol = 400mv l 1.8 3.4 ma sdo hi-z current l 1 a digital timing specifications (see figures 8 and 9) t ckh sclk high time l 25 ns t ckl sclk low time l 25 ns t css cs setup time l 10 ns t csh cs high time l 10 ns t cs sdi to sclk setup time l 6 ns t ch sdi to sclk hold time l 6 ns t do sclk to sdo time to v ih /v il /hi-z with 30pf load l 16 ns power supply voltages v ref + supply range l 3.15 3.3 3.45 v v refo + supply range l 3.15 3.3 3.45 v v d + supply range l 3.15 3.3 3.45 v v rf + supply range l 3.15 3.3 3.45 v v vco + supply range l 3.15 3.3 3.45 v v cp + supply range l 3.15 5.25 v power supply currents i dd v d + supply current digital inputs at supply levels l 500 a i cc(cp) v cp + supply current i cp = 11.2ma i cp = 1.0ma pdall = 1 l l l 34 12 235 39 14.5 385 ma ma a i cc(refo) v refo + supply currents refo enabled, r z = l 7.8 9.0 ma i cc sum v ref + , v rf + , v vco + supply currents rf muted, od[2:0] = 1 rf enabled, rfo[1:0] =0, od[2:0] = 1 rf enabled, rfo[1:0] = 3, od[2:0] = 1 rf enabled, rfo[1:0] =3, od[2:0] = 2 rf enabled, rfo[1:0] =3, od[2:0] = 3 rf enabled, rfo[1:0] =3, od[2:0] = 4 to 6 pdall = 1 l l l l l l l 70 79 88 105 111 116 202 78 88 98 117 124 128 396 ma ma ma ma ma ma a ltc6945 6945fa for more information www.linear.com/ltc6945
5 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v ref + = v ref0 + = v d + = v rf + = v vco + = 3.3v, v cp + = 5v unless otherwise specified. all voltages are with respect to gnd. symbol parameter conditions min typ max units phase noise and spurious l m(min) output phase noise floor (note 5) rfo[1:0] = 3, od[2:0] = 1, f rf = 6ghz rfo[1:0] = 3, od[2:0] = 2, f rf = 3ghz rfo[1:0] = 3, od[2:0] = 3, f rf = 2ghz rfo[1:0] = 3, od[2:0] = 4, f rf = 1.5ghz rfo[1:0] = 3, od[2:0] = 5, f rf = 1.2ghz rfo[1:0] = 3, od[2:0] = 6, f rf = 1.0ghz C155 C155 C156 C156 C157 C158 dbc /hz dbc/hz dbc/hz dbc/hz dbc/hz dbc/hz l m(norm) normalized in-band phase noise floor i cp = 11.2ma (notes 6, 7, 8) C226 dbc/hz l m(norm C1/f) normalized in-band 1/f phase noise i cp = 11.2ma (notes 6, 9) C274 dbc/hz l m(ib) in-band phase noise floor (notes 6, 7, 8, 10) C99 dbc/hz integrated phase noise from 100hz to 40mhz (notes 4, 7, 10) 0.13 rms spurious reference spur, pll locked (notes 4, 7, 10, 11) C102 dbc note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc6945i is guaranteed to meet specified performance limits over the full operating junction temperature range of C40c to 105c. under maximum operating conditions, air flow or heat sinking may be required to maintain a junction temperature of 105c or lower. it is strongly recommended that the exposed pad (pin 29) be soldered directly to the ground plane with an array of thermal vias as described in the applications information section. note 3: for 0.9v v cp (v cp + C 0.9v). note 4: vco is crystek cvco55cl-0902-0928. note 5: f vco = 6ghz, f offset = 40mhz. note 6: measured inside the loop bandwidth with the loop locked. note 7: reference frequency supplied by wenzel 501-04608a, f ref = 10mhz, p ref = 13dbm. note 8: output phase noise floor is calculated from normalized phase noise floor by l m(out) = C226 + 10log 10 (f pfd ) + 20log 10 (f rf /f pfd ). note 9: output 1/f phase noise is calculated from normalized 1/f phase noise by l m(out C1/f) = C274 + 20log 10 (f rf ) C 10log 10 (f offset ). note 10: i cp = 11.2ma, f pfd = 250khz, f rf = 914mhz, filt[1:0] = 3, loop bw = 7khz. note 11: measured using dc1649. typical p er f or m ance c harac t eris t ics ref input sensitivity vs frequency refo output power vs frequency refo phase noise frequency (mhz) 0 sensitivity (dbm) ?35 ?30 ?25 200 225 6945 g01 ?40 ?45 ?55 50 100 150 25 250 75 125 175 ?50 ?15 ?20 t j = 105c t j = 25c t j = ?40c bst = 1 filt = 0 frequency (mhz) 0 p out (dbm) 0 1 2 200 225 6945 g02 ?1 ?2 ?4 50 100 150 25 250 75 125 175 ?3 4 3 t j = 105c t j = 25c t j = ?40c offset frequency (hz) ?155 phase noise (dbc/hz) ?150 ?145 ?140 100 10k 100k 1m 5m 6945 g03 ?160 1k p out = 1.45dbm f ref = 10mhz bst = 1 filt = 3 note 7 ltc6945 6945fa for more information www.linear.com/ltc6945
6 charge pump sink current error vs voltage, output current charge pump sink current error vs voltage, temperature charge pump source current error vs voltage, output current typical p er f or m ance c harac t eris t ics charge pump source current error vs voltage, temperature rf output power vs frequency (single-ended on rf C ) rf output hd2 vs output divide (single-ended on rf C ) rf output hd3 vs output divide (single-ended on rf C ) mute output power vs f vco and output divide (single-ended on rf C ) frequency step transient output voltage (v) 0 error (%) 1 3 5 4 6945 g05 ?1 ?3 0 2 4 ?2 ?4 ?5 10.5 21.5 3 3.5 4.5 2.5 5 t j = 105c t j = 25c t j = ?40c i cp = 11.2ma output voltage (v) 0 error (%) 1 3 5 4 6945 g04 ?1 ?3 0 2 4 ?2 ?4 ?5 10.5 21.5 3 3.5 4.5 2.5 5 250a 1ma 11.2ma output voltage (v) 0 error (%) 1 3 5 4 6945 g06 ?1 ?3 0 2 4 ?2 ?4 ?5 10.5 21.5 3 3.5 4.5 2.5 5 250a 1ma 11.2ma output voltage (v) 0 error (%) 1 3 5 4 6945 g07 ?1 ?3 0 2 4 ?2 ?4 ?5 10.5 21.5 3 3.5 4.5 2.5 5 t j = 105c t j = 25c t j = ?40c i cp = 11.2ma frequency (ghz) 0 ?3.5 p out (dbm) ?3.0 ?2.0 ?1.5 ?1.0 3 3.5 4 54.5 5.5 1.0 6945 g08 ?2.5 0.5 1 1.5 2 2.5 6 ?0.5 0 0.5 t j = 105c t j = 25c t j = ?40c p vco = 0dbm l c = 180nh c s = 270pf time (s) 0 1.85 frequency (ghz) 1.90 2.00 2.05 2.10 10 20 25 45 6945 g12 1.95 5 15 30 35 40 f pfd = 1mhz bw = 40khz 100mhz step f vco (ghz) 0 hd3 (dbc) ?15 ?10 ?5 4 6945 g10 ?20 ?25 ?30 1 2 3 5 0.5 4.5 1.5 2.5 3.5 5.5 6 f rf = f vco /o p vco = 0dbm l c = 180nh c s = 270pf o = 6 o = 3 o = 2 o = 1 f vco (ghz) 0 ?120 p out at f vco /o (dbm) ?110 ?90 ?80 ?70 3 3.5 4 54.5 5.5 ?30 6945 g11 ?100 0.5 1 1.5 2 2.5 6 ?60 ?50 ?40 f rf = f vco /o p vco = 0dbm l c = 180nh c s = 270pf o = 1 o = 2 o = 3 o = 4 o = 5 o = 6 f vco (ghz) 0 ?55 hd2 (dbc) ?50 ?40 ?35 ?30 3 3.5 4 54.5 5.5 ?20 6945 g09 ?45 0.5 1 1.5 2 2.5 6 ?25 f rf = f vco /o p vco = 0dbm l c = 180nh c s = 270pf o = 3 o = 5 o = 1 o = 6 o = 2 o = 4 ltc6945 6945fa for more information www.linear.com/ltc6945
7 typical p er f or m ance c harac t eris t ics spurious response f rf = 914mhz, f ref = 10mhz, f pfd = 250khz, loop bw = 7khz spurious response f rf = 2100mhz, f ref = 10mhz, f pfd = 1mhz, loop bw = 40khz vco input sensitivity vs frequency, temperature closed-loop phase noise, f rf = 914mhz closed-loop phase noise, f rf = 2100mhz frequency (ghz) 0 sensitivity (dbm) ?15 ?10 4 6945 g13 ?20 ?25 ?30 ?35 1 2 3 5 0.5 4.5 1.5 2.5 3.5 5.5 6 t j = 105c t j = 25c t j = ?40c spurious response f rf = 5725mhz, f ref = 10mhz, f pfd = 5mhz, loop bw = 21khz supply current vs temperature frequency offset (mhz, in 10khz segments) ?10 ?3 ?2 ?1 0 21 3 10 ?140 p out (dbm) ?120 ?80 ?60 ?113dbc ?112dbc ?102dbc ?102dbc ?40 0 6945 g17 ?100 ?20 rbw = 1hz vbw = 1hz notes 7, 11 frequency offset (mhz, in 10khz segments) ?20 ?15 ?10 ?5 0 105 15 20 ?140 p out (dbm) ?120 ?80 ?60 ?112dbc ?112dbc ?100dbc ?101dbc ?40 0 6945 g18 ?100 ?20 rbw = 1hz vbw = 1hz notes 7, 11 frequency offset (mhz, in 10khz segments) ?10 ?0.75 ?0.5 ?0.25 0 0.50.25 0.75 10 ?140 p out (dbm) ?120 ?80 ?60 ?113dbc ?111dbc ?102dbc ?102dbc ?40 0 6945 g16 ?100 ?20 rbw = 1hz vbw = 1hz notes 7, 10, 11 temperature, t j (c) ?40 3.3v current (ma) 5v current (ma) 83 84 85 40 60 100 6945 g19 82 81 80 ?20 0 20 80 86 87 88 33.0 33.5 34.0 32.5 32.0 31.5 34.5 35.0 35.5 pdrefo = 1 o = 1 rfo = 3 mute = 0 i cp = 11.2ma offset frequency (hz) ?150 phase, noise (dbc/hz) ?140 ?120 ?100 ?90 100 10k 100k 6945 g14 ?160 1k 1m 10m 40m ?110 ?130 ?170 rms noise = 0.13 f pfd = 250khz bw = 7khz notes 7, 10 vco = crystek cvco55cl-0902-0928 offset frequency (hz) ?150 phase, noise (dbc/hz) ?140 ?120 ?100 ?90 100 10k 100k 6945 g15 ?160 1k 1m 10m 40m ?110 ?130 ?170 rms noise = 0.33 f pfd = 1mhz bw = 40khz note 7 vco = rfmd umx-586-d16-g ltc6945 6945fa for more information www.linear.com/ltc6945
8 v refo + (pin 1): 3.15 v to 3.45 v positive supply pin for refo circuitry. this pin should be bypassed directly to the ground plane using a 0.1 f ceramic capacitor as close to the pin as possible. refo (pin 2): reference frequency output. this produces a low noise square wave, buffered from the ref differential inputs. the output is self-biased and must be ac-coupled with a 22nf capacitor. s tat (pin 3): status output. this signal is a configurable logical or combination of the unlock, lock, thi and tlo status bits, programmable via the status register. see the operations section for more details. cs (pin 4): serial port chip select. this cmos input initi - ates a serial port communication burst when driven low, ending the burst when driven back high. see the operations section for more details. sclk (pin 5): serial port clock. this cmos input clocks serial port input data on its rising edge. see the operations section for more details. sdi (pin 6): serial port data input. the serial port uses this cmos input for data. see the operations section for more details. sdo (pin 7): serial port data output. this cmos three- state output presents data from the serial port during a read communication burst. optionally attach a resistor of >200 k to gnd to prevent a floating output. see the operations section for more details. v d + (pin 8): 3.15 v to 3.45 v positive supply pin for serial port circuitry. this pin should be bypassed directly to the ground plane using a 0.1 f ceramic capacitor as close to the pin as possible. mute (pin 9): rf mute. the cmos active-low input mutes the rf differential outputs while maintaining internal bias levels for quick response to de-assertion. gnd (pins 10, 17, 18, 19, 20, 21): negative power supply (ground). these pins should be tied directly to the ground plane with multiple vias for each pin. rf C , rf + (pins 11, 12): rf output signals. the vco output divider is buffered and presented differentially on these pins. the outputs are open collector, with 136 (typical) pull-up resistors tied to v rf + to aid impedance matching. if used single-ended, the unused output should be terminated to 50. see the applications information section for more details on impedance matching. v rf + (pin 13): 3.15 v to 3.45 v positive supply pin for rf circuitry. this pin should be bypassed directly to the ground plane using a 0.01 f ceramic capacitor as close to the pin as possible. bb (pin 14): rf reference bypass. this output must be bypassed with a 1.0 f ceramic capacitor to gnd. do not couple this pin to any other signal. vco C , vco + (pins 15, 16): vco input signals. the dif- ferential signal placed on these pins is buffered with a low noise amplifier and fed to the internal output and feedback dividers. these self-biased inputs must be ac-coupled and present a single-ended 121 ( typical) resistance to aid impedance matching. they may be used single- ended by bypassing vco C to gnd with a capacitor. see the applications information section for more details on impedance matching. v vco + (pin 22): 3.15 v to 3.45 v positive supply pin for vco circuitry. this pin should be bypassed directly to the ground plane using a 0.01 f ceramic capacitor as close to the pin as possible. gnd (23): negative power supply ( ground). this pin is attached directly to the die attach paddle ( dap) and should be tied directly to the ground plane. v cp + ( pin 24): 3.15 v to 5.25 v positive supply pin for charge pump circuitry. this pin should be bypassed directly to the ground plane using a 0.1 f ceramic capacitor as close to the pin as possible. cp ( pin 25): charge pump output. this bi-directional cur- rent o utput i s normally connected to the external loop filter . see the applications information section for more details. p in func t ions ltc6945 6945fa for more information www.linear.com/ltc6945
9 v ref + (pin 26): 3.15 v to 3.45 v positive supply pin for reference input circuitry. this pin should be bypassed directly to the ground plane using a 0.1 f ceramic capaci - tor as close to the pin as possible. ref + , ref C (pins 27, 28): reference input signals. this differential input is buffered with a low noise amplifier, which feeds the reference divider and reference buffer. they are self-biased and must be ac-coupled with 1f capacitors. if used single-ended, bypass ref C to gnd with a 1 f capacitor. if the single-ended signal is greater than 2.7v p-p , bypass ref C to gnd with a 47 pf capacitor. gnd ( exposed pad pin 29): negative power supply (ground). the package exposed pad must be soldered directly to the pcb land. the pcb land pattern should have multiple thermal vias to the ground plane for both low ground inductance and also low thermal resistance. p in func t ions b lock diagra m rf ? 28 2 3 11 gnd 10 mute 9 rf + 12 v rf + 13 27 ref ? refo 250mhz 100mhz 1 to 1023 1 to 6, 50% 32 to 65535 350mhz to 6ghz mute 1 v refo + ref + 26 v ref + r_div lock pfd o_div n_div 16 15 cp v vco + gnd gnd gnd gnd gnd vco + vco ? 250a to 11.2ma 25 22 21 20 19 18 17 24 v cp + 23 gnd 6945 bd 14 bb 350mhz to 6ghz serial port stat cs 7 sdo sdi sclk 8 v d + 6 5 4 ltc6945 6945fa for more information www.linear.com/ltc6945
10 o pera t ion figure 1. simplified ref interface schematic figure 2. simplified refo interface schematic the ltc6945 is a high performance pll, and, combined with an external high performance vco, can produce low noise lo signals up to 6 ghz. it is able to achieve superior integrated phase noise performance due to its extremely low in-band phase noise performance. reference input buffer the plls reference frequency is applied differentially on pins ref + and ref C . these high impedance inputs are self-biased and must be ac-coupled with 1 f capacitors (see figure 1 for a simplified schematic). alternatively, the inputs may be used single-ended by applying the refer - ence frequency at ref + and bypassing ref C to gnd with a 1 f capacitor. if the single-ended signal is greater than 2.7v p-p , then use a 47pf capacitor for the gnd bypass. table 1. filt[1:0] programming filt[1:0] f ref 3 <20mhz 2 na 1 20mhz to 50mhz 0 >50mhz table 2. bst programming bst v ref 1 <2.0v p-p 0 2.0v p-p reference output buffer the reference output buffer produces a low noise square wave with a noise floor of C155dbc/hz ( typical) at 10mhz. its output is low impedance, and produces 2 dbm typical output power into a 50 load at 10 mhz. larger output swings will result if driving larger impedances. the out - put is self-biased, and must be ac-coupled with a 22nf capacitor ( see figure 2 for a simplified schematic). the buffer may be powered down by using bit pdrefo found in the serial port power register h02. 27 28 4.2k ref + ref ? bst filt[1:0] lowpass 4.2k 6945 f01 1.9v bias v ref + v ref + a high quality signal must be applied to the ref inputs as they provide the frequency reference to the entire pll. to achieve the parts in-band phase noise performance, apply a cw signal of at least 6 dbm into 50, or a square wave of at least 0.5v p-p with slew rate of at least 40v/s. additional options are available through serial port register h08 to further refine the application. bits filt[1:0] control the reference input buffers lowpass filter, and should be set based upon f ref to limit the references wideband noise. the filt[1:0] bits must be set correctly to reach the l m(norm) normalized in-band phase noise floor. see table 1 for recommended settings. the bst bit should be set based upon the input signal level to prevent the reference input buffer from saturating. see table 2 for recommended settings and the applications information section for programming examples. 2 refo v refo + 800 6945 f02 reference (r) divider a 10- bit divider, r_div, is used to reduce the frequency seen at the pfd. its divide ratio r may be set to any integer from 1 to 1023, inclusive. use the rd[9:0] bits found in registers h03 and h04 to directly program the r divide ratio. see the applications information section for the relationship between r and the f ref , f pfd , f vco and f rf frequencies. ltc6945 6945fa for more information www.linear.com/ltc6945
11 o pera t ion figure 3. simplified pfd schematic figure 4. unlock and lock timing phase/frequency detector (pfd) the phase/frequency detector ( pfd), in conjunction with the charge pump, produces source and sink current pulses proportional to the phase difference between the outputs of the r and n dividers. this action provides the necessary feedback to phase-lock the loop, forcing a phase align - ment at the pfds inputs. the pfd may be disabled with the cprst bit which prevents up and down pulses from being produced. see figure 3 for a simplified schematic of the pfd. the user sets the phase difference lock window time, t lww , for a valid lock condition with the lkwin[1:0] bits. see table 3 for recommended settings for different f pfd frequencies and the applications information section for examples. table 3. lkwin[1:0] programming lkwin[1:0] t lww f pfd 0 3ns >5mhz 1 10ns 5mhz 2 30ns 1.7mhz 3 90ns 550khz the pfd phase difference must be less than t lww for the counts number of successive counts before the lock indicator asserts the lock flag. the lkct[1:0] bits found in register h09 are used to set counts depending upon the application. see table 4 for lkct[1:0] programming and the applications information section for examples. table 4. lkct[1:0] programming lkct[1:0] counts 0 32 1 128 2 512 3 2048 when the pfd phase difference is greater than t lww , the lock indicator immediately asserts the unlock status flag and clears the lock flag, indicating an out-of-lock condition. the unlock flag is immediately de-asserted when the phase difference is less than t lww . see figure 4 for more details. d q rst n div d q rst cprst up down 6945 f03 delay r div lock indicator the lock indicator uses internal signals from the pfd to measure phase coincidence between the r and n divider output signals. it is enabled by setting the lken bit in the serial port register h07, and produces both lock and unlock status flags, available through both the stat output and serial port register h00. +t lww ?t lww unlock flag lock flag t = counts/f pfd 6945 f04 0 phase difference at pfd ltc6945 6945fa for more information www.linear.com/ltc6945
12 o pera t ion figure 5. simplified charge pump schematic charge pump the charge pump, controlled by the pfd, forces sink (down) or source ( up) current pulses onto the cp pin, which should be connected to an appropriate loop filter. see figure 5 for a simplified schematic of the charge pump. as for loops using negative-slope tuning oscillators, or inverting op amps in conjunction with positive - slope tuning oscillators. a passive loop filter as shown in figure 15, used in conjunction with a positive-slope vco, requires cpinv = 0. charge pump functions the charge pump contains additional features to aid in system start-up and monitoring. see table 6 for a summary. table 6. cp function bit descriptions bit description cpchi enable high voltage output clamp cpclo enable low voltage output clamp cpdn force sink current cpinv invert pfd phase cpmid enable mid-voltage bias cprst reset pfd cpup force source current cpwide extend current pulse width thi high voltage clamp flag tlo low voltage clamp flag the cpchi and cpclo bits found in register h0a enable the high and low voltage clamps, respectively. when cpchi is enabled and the cp pin voltage exceeds ap - proximately v cp + C 0.9 v, the thi status flag is set, and the charge pump sourcing current is disabled. alternately, when cpclo is enabled and the cp pin voltage is less than approximately 0.9 v, the tlo status flag is set, and the charge pump sinking current is disabled. see figure 5 for a simplified schematic. the cpmid bit also found in register h0a enables a resistive v cp + /2 output bias which may be used to pre- bias troublesome loop filters into a valid voltage range before attempting to lock the loop. when using cpmid, it is recommended to also assert the cprst bit, forcing a pfd reset. both cpmid and cprst must be set to 0 for normal operation. the cpup and cpdn bits force a constant i cp source or sink current, respectively, on the cp pin. the cprst bit may also be used in conjunction with the cpup and cpdn 25 + ? + ? cp thi 0.9v v cp + v cp + tlo + ? 0.9v 6945 f05 + ? v cp + /2 cpmid cpup up cpdn down the output current magnitude i cp may be set from 250 a to 11.2ma using the cp[3:0] bits found in serial port register h09. a larger i cp can result in lower in-band noise due to the lower impedance of the loop filter components. see table 5 for programming specifics and the applications information section for loop filter examples. table 5. cp[3:0] programming cp[3:0] i cp 0 250a 1 350a 2 500a 3 700a 4 1.0ma 5 1.4ma 6 2.0ma 7 2.8ma 8 4.0ma 9 5.6ma 10 8.0ma 11 11.2ma 12 to 15 invalid the cpinv bit found in register h0a should be set for ap- plications requiring signal inversion from the pfd, such ltc6945 6945fa for more information www.linear.com/ltc6945
13 o pera t ion figure 7. simplified rf interface schematic bits, allowing a pre-charge of the loop to a known state, if required. cpup, cpdn, and cprst must be set to 0 to allow the loop to lock. the cpwide bit extends the charge pump output current pulse width by increasing the pfd reset paths delay value (see figure 3). cpwide is normally set to 0. vco input buffer the vco frequency is applied differentially on pins vco + and vco C . the inputs are self-biased and must be ac-coupled. alternatively, the inputs may be used single-ended by ap- plying the vco frequency at vco + and bypassing vco C to gnd with a capacitor. each input provides a single-ended output (o) divider the 3- bit o divider can reduce the frequency from the vco input buffer to the rf output buffer to extend the output frequency range. its divide ratio o may be set to any in - teger from 1 to 6, inclusive, outputting a 50% duty cycle even with odd divide values. use the od[2:0] bits found in register h08 to directly program the 0 divide ratio. see the applications information section for the relationship between o and the f ref , f pfd , f vco and f rf frequencies. rf output buffer the low noise, differential output buffer produces a dif- ferential output power of C6 dbm to 3 dbm, settable with bits rfo[1:0] according to table 7. the outputs may be combined externally, or used individually. terminate any unused output with a 50 resistor to v rf + . table 7. rfo[1:0] programming rfo[1:0} p rf (differential) p rf (single-ended) 0 C6dbm C9dbm 1 C3dbm C6dbm 2 0dbm C3dbm 3 3dbm 0dbm each output is open collector with 136 pull-up resistors to v rf + , easing impedance matching at high frequencies. see figure 7 for circuit details and the applications infor- mation section for matching guidelines. the buffer may be muted with either the omute bit, found in register h02, or by forcing the mute input low. 16 15 121 vco + vc0 ? 121 6945 f06 0.9v v vco + v vco + v vco + + ? figure 6. simplified vco interface schematic 121 resistance to aid in impedance matching at high frequencies. see the applications information section for matching guidelines. vco (n) divider the 16- bit n divider provides the feedback from the vco input buffer to the pfd. its divide ratio n may be set to any integer from 32 to 65535, inclusive. use the nd[15:0] bits found in registers h05 and h06 to directly program the n divide ratio. see the applications information section for the relationship between n and the f ref , f pfd , f vco and f rf frequencies. 12 11 6945 f07 v rf + v rf + rf + 136 136 rf ? mute omute rfo[1:0] 9 mute ltc6945 6945fa for more information www.linear.com/ltc6945
14 o pera t ion serial port the spi-compatible serial port provides control and moni- toring functionality . a configurable status output, stat , gives additional instant monitoring. communication sequence the serial bus is comprised of cs , sclk, sdi and sdo. data transfers to the part are accomplished by the se - rial bus master device first taking cs low to enable the ltc6945s port. input data applied on sdi is clocked on the rising edge of sclk, with all transfers msb first. the communication burst is terminated by the serial bus master returning cs high. see figure 8 for details. data is read from the part during a communication burst using sdo. readback may be multidrop ( more than one ltc6945 connected in parallel on the serial bus), as sdo is three-stated ( hi-z) when cs = 1, or when data is not being read from the part. if the ltc 6945 is not used in a multidrop configuration, or if the serial port master is not capable of setting the sdo line level between read sequences, it is recommended to attach a high value resistor of greater than 200 k between sdo and gnd to ensure the line returns to a known level during hi-z states. see figure 9 for details. single byte t ransfers the serial port is arranged as a simple memory map, with status and control available in 12, byte-wide registers. all data bursts are comprised of at least two bytes. the 7 most significant bits of the first byte are the register address, with an lsb of 1 indicating a read from the part, and lsb of 0 indicating a write to the part. the subsequent byte, or bytes, is data from/to the specified register address. see figure 10 for an example of a detailed write sequence, and figure 11 for a read sequence. figure 12 shows an example of two write communication bursts. the first byte of the first burst sent from the serial bus master on sdi contains the destination register address (addr0) and an lsb of 0 indicating a write. the next byte is the data intended for the register at address addr0. cs is then taken high to terminate the transfer. the first byte of the second burst contains the destination register address (addr1) and an lsb indicating a write. the next byte on sdi is the data intended for the register at address addr1. cs is then taken high to terminate the transfer. figure 8. serial port write timing diagram figure 9. serial port read t iming diagram master?cs master?sclk t css t cs t ch data data 6945 f07 t ckl t ckh t css t csh master?sdi master?cs master?sclk ltc6945?sdo hi-z hi-z 6945 f09 8th clock data data t do t do t do t do ltc6945 6945fa for more information www.linear.com/ltc6945
15 o pera t ion figure 10. serial port write sequence figure 11. serial port read sequence figure 12. serial port single byte write multiple byte transfers more efficient data transfer of multiple bytes is accom- plished by using the ltc6945s register address auto- increment feature as shown in figure 13. the serial port master sends the destination register address in the first byte and its data in the second byte as before, but continues sending bytes destined for subsequent registers. byte 1s address is addr0+1, byte 2 s address is addr0+2, and so on. if the resister address pointer attempts to increment past 11 (h0b), it is automatically reset to 0. an example of an auto-increment read from the part is shown in figure 14. the first byte of the burst sent from the serial bus master on sdi contains the destination register address ( addr0) and an lsb of 1 indicating a read. once the ltc6945 detects a read burst, it takes sdo out of the hi -z condition and sends data bytes sequentially, beginning with data from register addr0. the part ignores all other data on sdi until the end of the burst. multidrop configuration several ltc6945 s may share the serial bus. in this multidrop configuration, sclk, sdi and sdo are com- mon between all parts. the serial bus master must use a separate cs for each ltc6945 and ensure that only one device has cs asserted at any time. it is recommended to attach a high value resistor to sdo to ensure the line returns to a known level during hi-z states. a6 a5 a4 a3 a2 7-bit register address hi-z master?cs master?sclk master?sdi ltc6945?sd0 a1 a0 0 d7 d6 d5 d4 d3 d2 d1 d0 8 bits of data 0 = write 6945 f10 16 clocks a6 a5 a4 a3 a2 7-bit register address hi-z hi-z a1 a0 1 d7x d6 d5 d4 d3 d2 d1 d0 dx 8 bits of data 1 = read 6945 f11 master?cs master?sclk master?sdi ltc6945?sdo 16 clocks addr0 + wr hi-z master?cs master?sdi ltc6945?sdo byte 0 addr1 + wr byte 1 6945 f12 ltc6945 6945fa for more information www.linear.com/ltc6945
16 o pera t ion figure 13. serial port auto-increment write figure 14. serial port auto-increment read addr0 + wr hi-z master?cs master?sdi ltc6945?sdo byte 0 byte 1 byte 2 6945 f12 addr0 + rd don?t care hi-z hi-z master?cs master?sdi ltc6945?sdo 6945 f13 byte 0 byte 1 byte 2 serial port registers the memory map of the ltc6945 may be found in table 8, with detailed bit descriptions found in table 9. the register address shown in hexadecimal format under the addr column is used to specify each register. each register is denoted as either read-only ( r) or read-write ( r/w). the registers default value on device power-up or after a reset is shown at the right. the read-only register at address h00 is used to determine different status flags. these flags may be instantly output on the stat pin by configuring register h01. see the stat output section for more information. the read-only register at address h0b is a rom byte for device identification. s tat output the stat output pin is configured with the x[5:0] bits of register h01. these bits are used to bit-wise mask, or enable, the corresponding status flags of status register h00, according to equation 1. the result of this bit-wise boolean operation is then output on the stat pin: stat = or (reg00[5,2:0] and reg01[5,2:0]) (1) or expanded: stat = (unlock and x[5]) or ( lock and x[2]) or ( thi and x[1]) or ( tlo and x[0]) for example, if the application requires s tat to go high whenever the lock or thi flags are set, then x[2] and x[1] should be set to 1, giving a register value of h6. block power-down control the ltc6945s power-down control bits are located in register h02, described in table 9. different portions of the device may be powered down independently. care must be taken with the lsb of the register, the por ( power-on reset) bit. when written to a 1, this bit forces a full reset of the parts digital circuitry to its power-up default state. ltc6945 6945fa for more information www.linear.com/ltc6945
17 o pera t ion table 9. serial port register bit field summary table 8. serial port register contents addr msb [6] [5] [4] [3] [2] [1] lsb r/w default h00 * * unlock * * lock thi tlo r h01 * * x[5] * * x[2] x[1] x[0] r/w h04 h02 pdall pdpll * pdout pdrefo * omute por r/w h0e h03 * * * * * * rd[9] rd[8] r/w h00 h04 rd[7] rd[6] rd[5] rd[4] rd[3] rd[2] rd[1] rd[0] r/w h01 h05 nd[15] nd[14] nd[13] nd[12] nd[11] nd[10] nd[9] nd[8] r/w h00 h06 nd[7] nd[6] nd[5] nd[4] nd[3] nd[2] nd[1] nd[0] r/w hfa h07 * * * * * * * lken r/w h01 h08 bst filt[1] filt[0] rfo[1] rfo[0] od[2] od[1] od[0] r/w hf9 h09 lkwin[1] lkwin[0] lkct[1] lkct[0] cp[3] cp[2] cp[1] cp[0] r/w h9b h0a cpchi cpclo cpmid cpinv cpwide cprst cpup cpdn r/w he4 h0b rev[2] rev[1] rev[0] part [4] part [3] part [2] part [1] part [0] r h40 *unused bits description default bst ref buffer boost current 1 cp[3:0] cp output current hb cpchi cp enable hi voltage output clamp 1 cpclo cp enable low voltage output clamp 1 cpdn cp pump down only 0 cpinv cp invert phase 0 cpmid cp bias to mid-rail 1 cprst cp three-state 1 cpup cp pump up only 0 cpwide cp extend pulse width 0 filt[1:0] ref input buffer filter h3 lkct[1:0] pll lock cycle count h1 lken pll lock indicator enable 1 lkwin[1:0] pll lock indicator window h2 lock pll lock indicator flag nd[15:0] n divider value (nd[15:0] > 31) h00fa bits description default od[2:0] output divider value (0 < od[2:0] < 7) h1 omute mutes rf output 1 part [4:0] part code h00 pdall full chip power-down 0 pdout powers down o_div, rf output buffer 0 pdpll powers down ref, refo, r_div, pfd, cpump, n_div 0 pdrefo powers down refo 1 por force power-on reset register initialization 0 rd[9:0] r divider value (rd[9:0] > 0) h001 rev[2:0] rev code rfo[1:0] rf output power h3 thi cp clamp high flag tlo cp clamp low flag unlock pll unlock flag x[5,2:0] stat output or mask h04 ltc6945 6945fa for more information www.linear.com/ltc6945
18 a pplica t ions i n f or m a t ion introduction a pll is a complex feedback system that may conceptually be considered a frequency multiplier. the system multiplies the frequency input at ref and outputs a higher frequency at rf . the pfd, charge pump, n divider, and external vco and loop filter form a feedback loop to accurately control the output frequency ( see figure 15). the r and o dividers are used to set the output frequency resolution. using the above equations, the output frequency resolution f step produced by a unit change in n is given by equation 5: f step = f ref r ? o (5) loop fil ter design a stable pll system requires care in selecting the external loop filter values. the linear technology pllwizard ap- plication, available from www.linear.com, aids in design and simulation of the complete system. the loop design should use the following algorithm: 1. determine the output frequency, f rf , and frequency step size, f step , based on application constraints. using equations 2, 3, 4 and 5, change f ref , n, r and o until the application frequency constraints are met. use the minimum r value that still satisfies the constraints. 2. select the loop bandwidth bw constrained by f pfd . a stable loop requires that bw is less than f pfd by at least a factor of 10. 3. select loop filter component r z and charge pump cur- rent i cp based on bw and the vco gain factor k vco . bw ( in hz) is approximated by the following equation: bw ? i cp ? r z ? k vco 2 ? ? n or : r z = 2 ? ? bw ? n i cp ? k vco (6) where k vco is in hz/v, i cp is in amps, and r z is in ohms. k vco is the vcos frequency tuning sensitivity, and may be determined from the vco specifications. use i cp = 11.2 ma to lower in-band noise unless component values force a lower setting. figure 15. pll loop diagram r_div n_div r n o f pfd ltc6945 ref (f ref ) (f vco ) k pfd k vco rf (f rf ) cp r z c i c p loop filter lf(s) 6945 f15 vco i cp o_div output frequency when the loop is locked, the frequency f vco ( in hz) produced at the output of the vco is determined by the reference frequency f ref , and the r and n divider values, given by equation 2: f vco = f ref ? n r (2) here, the pfd frequency f pfd produced is given by the following equation: f pfd = f ref r (3) and f vco may be alternatively expressed as: f vco = f pfd ? n the output frequency f rf produced at the output of the o divider is given by equation 4: f rf = f vco o (4) ltc6945 6945fa for more information www.linear.com/ltc6945
19 a pplica t ions i n f or m a t ion 4. select loop filter components c i and c p based on bw and r z . a reliable loop can be achieved by using the following equations for the loop capacitors ( in farads): c i = 3.5 2 ? ? bw ? r z (7) c p = 1 7 ? ? bw ? r z (8) loop fil ters using an opamp some vco tune voltage ranges are greater than the ltc6945 s charge pump voltage range. an active loop filter using an op amp can increase the tuning voltage range. to maintain the ltc6945s high performance, care must be given to picking an appropriate op amp. the op amp input common mode voltage should be biased within the ltc6945 charge pumps voltage range, while its output voltage should achieve the vco tuning range. see figure 16 for an example op amp loop filter. the op amps input bias current is supplied by the charge pump; minimizing this current keeps spurs related to f pfd low. the input bias current should be less than the charge pump leakage ( found in the electrical characteristics sec - tion) to avoid increasing spurious products. op amp noise sources are highpass filtered by the pll loop filter and should be kept at a minimum, as their ef- fect raises the total system phase noise beginning near the loop bandwidth. choose a low noise op amp whose input-referred voltage noise is less than the thermal noise of r z . additionally, the gain bandwidth of the op amp should be at least 15 times the loop bandwidth to limit phase margin degradation. the lt1678 is an op amp that works very well in most applications. an additional r-c lowpass filter ( formed by r p2 and c p2 in figure 16) connected at the input of the vco will limit the op amp noise sources. the bandwidth of this filter should be placed approximately 15 to 20 times the pll loop bandwidth to limit loop phase margin degradation. r p2 should be small ( preferably much less than r z ) to minimize its noise impact on the loop. however, picking too small of a value can make the op amp unstable as it has to drive the capacitor in this filter. design and programming example this programming example uses the dc1649. assume the following parameters of interest : f ref = 100mhz at 7dbm into 50 f step = 250khz f vco = 902mhz to 928mhz k vco = 15mhz/v to 21.6mhz/v f rf = 914mhz determining divider values following the loop filter design algorithm, first determine all the divider values. using equations 2, 3, 4 and 5, cal - culate the following values: o = 1 r = 100mhz/250khz = 400 f pfd = 250khz n = 914mhz/250khz = 3656 figure 16. op amp loop filter c p loop filter lf(s) c i c p2 k vco 6945 f16 47f cp i cp vco (f vco ) v cp + /2 5k 5k v cp + ltc6945 r z r p2 ? + ltc6945 6945fa for more information www.linear.com/ltc6945
20 the next step in the algorithm is to determine the open- loop bandwidth. bw should be at least 10 smaller than f pfd . wider loop bandwidths could have lower integrated phase noise, depending on the vco phase noise signature, while narrower bandwidths will likely have lower spurious power. use a factor of 25 for this design: bw = 250khz 25 = 10kh z loop filter component selection now set loop filter resistor r z and charge pump current i cp . because the k vco varies over the vcos frequency range, using the k vco geometric mean gives good results. using an i cp of 11.2ma, r z is determined: k vco = 10 6 ? 15 ? 21.6 = 18mhz / v r z = 2 ? ? 10k ? 3656 11.2m ? 18m r z = 1.14k now calculate c i and c p from equations 7 and 8: c i = 3.5 2 ? ? 10k ? 1.14k = 48.9nf c p = 1 7 ? ? 10k ? 1.14k = 3.99n f status output programming this example will use the stat pin to monitor a phase lock condition. program x [2] = 1 to force the stat pin high whenever the lock bit asserts: reg01 = h04 power register programming for correct pll operation all internal blocks should be enabled, but pdrefo should be set if the refo pin is not being used. omute may remain asserted ( or the mute pin held low) until programming is complete. for pdrefo = 1 and omute = 1: reg02 = h0a divider programming program registers reg03 to reg06 with the previously determined r and n divider values: reg03 = h01 reg04 = h90 reg05 = h0e reg06 = h48 reference input settings and output divider programming from table 1, filt = 0 for a 100 mhz reference frequency. next, convert 7 dbm into v p-p . for a cw tone, use the following equation with r = 50: v p-p ? r ? 10 (dbm C 21)/20 (9) this gives v p-p = 1.41 v, and, according to table 2, set bst = 1. now program reg08, assuming maximum rf output power ( rfo[1:0] = 3 according to table 7) and od[2:0] = 1: reg08 = h99 lock detect and charge pump current programming next determine the lock indicator window from f pfd . from table 3, lkwin [1:0] = 3 for a t lww of 90 ns. the ltc6945 will consider the loop locked as long as the phase coincidence at the pfd is within 8, as calculated below: phase = 360 ? t lww ? f pfd = 360 ? 90n ? 250k ? 8 lkwin[1:0] may be set to a smaller value to be more conservative. however, the inherent phase noise of the loop could cause false unlocks for too small a value. choosing the correct counts depends upon the ratio of the bandwidth of the loop to the pfd frequency (bw/f pfd ). smaller ratios dictate larger counts values. a counts value of 128 will work for the ratio of 1/25. from table 4, lkct[1:0] = 1 for 128 counts. a pplica t ions i n f or m a t ion ltc6945 6945fa for more information www.linear.com/ltc6945
21 a pplica t ions i n f or m a t ion using table 5 with the previously selected i cp of 11.2ma, gives cp [3:0] = 11. this is enough information to program reg09: reg09 = hdb to enable the lock indicator, write reg07: reg07 = h01 charge pump function programming the dc1649 includes an lt1678i op amp in the loop filter. this allows the circuit to reach the voltage range speci - fied for the vcos tuning input. however, it also adds an inversion in the loop transfer function. compensate for this inversion by setting cpinv = 1. this example does not use the additional voltage clamp features to allow fault condition monitoring. the loop feedback provided by the op amp will force the charge pump output to be equal to the op amp positive input pins voltage. disable the charge pump voltage clamps by setting cpchi = 0 and cpclo = 0. disable all the other charge pump functions ( cpmid, cprst, cpup and cpdn) to allow the loop to lock: reg0a = h10 the loop should now lock. now unmute the output by setting omute = 0 (assumes the mute pin is high): reg02 = h08 reference source considera tions a high quality signal must be applied to the ref inputs as they provide the frequency reference to the entire pll. as mentioned previously, to achieve the parts in-band phase noise performance, apply a cw signal of at least 6dbm into 50, or a square wave of at least 0.5v p-p with slew rate of at least 40v/s. the ltc6945 may be driven single-ended to cmos levels (greater than 2.7v p-p ). apply the reference signal directly without a dc-blocking capacitor at ref + , and bypass ref C to gnd with a 47 pf capacitor. the bst bit must also be set to 0, according to guidelines given in table 2. the ltc6945 achieves an in- band normalized phase noise floor of C226 dbc/hz (typical). to calculate its equivalent input phase noise floor l m(in) , use equation 10: l m(in) = C226 + 10 ? log 10 (f ref ) (10) for example, using a 10 mhz reference frequency gives an input phase noise floor of C156 dbc/hz. the reference frequency sources phase noise must be approximately 3db better than this to prevent limiting the overall system performance. in-band output phase noise the in-band phase noise produced at f rf may be calculated by using equation 11. l m(out) = C226 + 10 ? log 10 f pfd ( ) + 20 ? log 10 f rf f pfd ? ? ? ? ? ? or l m(out) = C226 + 10 ? log 10 f pfd ( ) + 20 ? log 10 n o ? ? ? ? ? ? (11) as seen for a given pfd frequency f pfd , the output in-band phase noise increases at a 20 db-per-decade rate with the n divider count. so, for a given output frequency f rf , f pfd should be as large as possible ( or n should be as small as possible) while still satisfying the applications frequency step size requirements. output phase noise due to 1/f no ise in-band phase noise at very low offset frequencies may be influenced by the ltc6945s 1/ f noise, depending upon f pfd . use the normalized in-band 1/ f noise of C274 dbc/hz with equation 12 to approximate the output 1/ f phase noise at a given frequency offset f offset : l m(out C1/f) (f offset ) = C274 + 20 ? log 10 (f rf ) (12) C 10 ? log 10 (f offset ) ltc6945 6945fa for more information www.linear.com/ltc6945
22 a pplica t ions i n f or m a t ion unlike the in-band noise floor l m(out) , the 1/ f noise l m(out C1/f) does not change with f pfd and is not constant over offset frequency. see figure 17 for an example of in-band phase noise for f pfd equal to 3 mhz and 100mhz. the total phase noise will be the summation of l m(out) and l m(out C1/f) . vco input matching the vco inputs may be used differentially or single - ended . each input provides a single-ended 121 resistance to aid in impedance matching at high frequencies. the inputs are self-biased and must be ac-coupled using a 100 pf capaci - tors (or 270pf for vco frequencies less than 500mhz). the inputs may be used single-ended by applying the ac - coupled vco frequency at vco + and bypassing vco C to gnd with a 100 pf capacitor (270 pf for frequen- cies less than 500 mhz). measured vco + s-parameters (with vco C bypassed with 100 pf to gnd) are shown in table 10 to aid in the design of external impedance match- ing networks. rf output ma tching the rf outputs may be used in either single-ended or differential configurations. using both rf outputs differen- tially will result in approximately 3 db more output power than single-ended. impedance matching to an external load in both cases requires external chokes tied to v rf + . measured rf s-parameters are shown below in table 11 to aid in the design of impedance matching networks. figure 17. theoretical in-band phase noise, f rf = 2500mhz offset frequency (hz) ?120 phase noise (dbc/hz) ?90 10 100 10k 100k 6945 f17 1k ?100 ?110 ?130 total noise f pfd = 3mhz total noise f pfd = 100mhz 1/f noise contribution table 10. single-ended vco + input impedance frequency (mhz) impedance () s11 (db) 250 118 C j78 C5.06 500 83.6 C j68.3 C5.90 1000 52.8 C j56.1 C6.38 1500 35.2 C j41.7 C6.63 2000 25.7 C j30.2 C6.35 2500 19.7 C j20.6 C5.94 3000 17.6 C j11.2 C6.00 3500 17.8 C j3.92 C6.41 4000 19.8 + j4.74 C7.20 4500 21.5 + j15.0 C7.12 5000 21.1 + j19.4 C6.52 5500 27.1 + j22.9 C7.91 6000 38.3 + j33.7 C8.47 6500 36.7 + j42.2 C6.76 7000 46.2 + j40.9 C8.11 7500 76.5 + j36.8 C9.25 8000 84.1+ j52.2 C7.27 table 11. single-ended rf output impedance frequency (mhz) impedance () s11 (db) 500 102.8 C j49.7 C6.90 1000 70.2 C j60.1 C6.53 1500 52.4 C j56.2 C6.35 2000 43.6 C j49.2 C6.58 2500 37.9 C j39.6 C7.34 3000 32.7 C j28.2 C8.44 3500 27.9 C j17.8 C8.99 4000 24.3 C j9.4 C8.72 4500 22.2 C j3.3 C8.26 5000 21.6 + j1.9 C8.02 5500 21.8 + j6.6 C7.91 6000 23.1 + j11.4 C8.09 6500 25.7 + j16.9 C8.38 7000 29.3 + j23.0 C8.53 7500 33.5 + j28.4 C8.56 8000 37.9 + j32.6 C8.64 ltc6945 6945fa for more information www.linear.com/ltc6945
23 a pplica t ions i n f or m a t ion figure 19. single-ended return loss figure 18. single-ended output matching schematic for lower frequencies, transmission line ( tl) baluns such as the m/a-com mabact0065 and the toko #617 db-1673 provide good results. at higher frequencies, surface mount (smt) baluns such as those produced by tdk, anaren, and johanson technology, can be attractive alternatives. see table 13 for recommended balun part numbers versus frequency range. the listed smt baluns contain internal chokes to bias rf and also provide input-to-output dc isolation. the pin denoted as gnd or dc feed should be connected to the v rf + voltage. figure 20 shows a surface mount baluns connections with a dc feed pin. rf +(?) l c c s 50 to 50 load v rf + rf ?(+) l c c s 6945 f18 v rf + 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 frequency (ghz) s11 (db) ?6 ?4 ?2 6945 f19 ?10 ?16 0 ?8 ?12 ?14 68nh, 100pf 180nh, 270pf single-ended impedance matching is accomplished using the circuit of figure 18, with component values found in table 12. using smaller inductances than recommended can cause phase noise degradation, especially at lower center frequencies. table 12. suggested single-ended matching component values f rf (mhz) l c (nh) c s (pf) 350 to 1500 180nh 270pf 1000 to 5800 68nh 100pf return loss measured on the dc1649 using the above component values is shown in figure 19. a broadband match is achieved using an ( l c , c s ) of either (68nh, 100pf) or (180nh, 270 pf). however, for maximum output power and best phase noise performance, use the recommended component values of table 12. l c should be a wirewound inductor selected for maximum q factor and srf, such as the coilcraft hp series of chip inductors. the ltc6945s differential rf outputs may be combined using an external balun to drive a single-ended load. the advantages are approximately 3 db more output power than each output individually and better 2 nd-order harmonic performance. figure 20. example of a smt balun connection ltc6945 v rf + rf ? rf + to 50 load 6945 f20 12 balun 2 3 1 5 4 6 11 balun pin configuration 1 2 3 4 5 6 unbalanced port gnd or dc feed balanced port balanced port gnd nc ltc6945 6945fa for more information www.linear.com/ltc6945
24 a pplica t ions i n f or m a t ion figure 22. example exposed pad land pattern table 13. suggested baluns f rf (mhz) part number manufacturer type 350 to 900 #617db-1673 toko tl 400 to 600 hhm1589b1 tdk smt 600 to 1400 bd0810j50200 anaren smt 600 to 3000 mabact0065 m/a-com tl 1000 to 2000 hhm1518a3 tdk smt 1400 to 2000 hhm1541e1 tdk smt 1900 to 2300 2450bl15b100e johanson smt 2000 to 2700 hhm1526 tdk smt 3700 to 5100 hhm1583b1 tdk smt 4000 to 6000 hhm1570b1 tdk smt the listed tl baluns do not provide input-to-output dc isolation and must be ac coupled at the output. figure 21 displays rf connections using these baluns. figure 21. example of a tl balun connection ltc6945 v rf + rf ? rf + to 50 load pri sec 6945 f21 12 11 6945 f22 reference signal routing and spurious the charge pump operates at the pfds update frequency f pfd . the resultant output spurious energy is small and is further reduced by the loop filter before it modulates the vco frequency. however, improper pcb layout can degrade the ltc6945 s inherent spurious performance. care must be taken to prevent the reference signal f ref from coupling onto the vcos tune line, or into other loop filter signals. example suggestions are the following. 1. do not share power supply decoupling capacitors between same voltage power supply pins. 2. use separate ground vias for each power supply decou - pling capacitor, especially those connected to v ref + , v cp + , and v vco + . 3. physically separate the reference frequency signal from the loop filter and vco. supply bypassing and pcb layout guidelines care must be taken when creating a pcb layout to mini - mize power supply decoupling and ground inductances. all power supply v + pins should be bypassed directly to the ground plane using a 0.1 f ceramic capacitor as close to the pin as possible. multiple vias to the ground plane should be used for all ground connections, including to the power supply decoupling capacitors. the packages exposed pad is a ground connection, and must be soldered directly to the pcb land. the pcb land pattern should have multiple thermal vias to the ground plane for both low ground inductance and also low thermal resistance ( see figure 22 for an example). see qfn pack - age users guide, page 8, on linear technology websites packaging information page for specific recommendations concerning land patterns and land via solder masks. links are provided below. http://www.linear.com/designtools/packaging ltc6945 6945fa for more information www.linear.com/ltc6945
25 ltc6945 wideband frequency hopping local oscillator typical a pplica t ions frequency hopping lo out frequency, lo1 = 450mhz, lo2 = 700mhz time (s) ?0.6 lo out frequency (mhz) mute voltages (v) 3 450 0 0.4 6945 ta02b 2 1 0 ?0.4 ?0.2 0.2 550 650 750 0.6 mute1 mute2 frequency hopping lo out power, lo1 = 450mhz, lo2 = 700mhz frequency hopping lo out spectrum, lo1 = 450mhz muted, lo2 = 700mhz frequency (mhz) 400 power (dbm) ?80 ?20 ?10 0 500 600 650 6945 ta02d ?100 ?40 ?60 ?90 ?30 ?110 ?50 ?70 450 550 700 750 f pfd = 1mhz od = 2 ?95dbc v vco + gnd gnd gnd gnd gnd vco + vco ? v refo + refo stat cs sclk sdi sdo v d + mute gnd rf ? gnd ltc6945 o_div = 2 rf + v rf + bb ref ? 3.3v 0.1f 100mhz ref ref + v ref + cp v cp + gnd + 0.01f 100pf 700mhz to 1400mhz 1.0f 22nf lt1678is8 274 4.99k 4.99k 267nf 1f 0.1f 0.1f 47f 1f 3.3v 3.3v spi bus mute1 0.1f 0.01f 180nh 180nh 3.3v 3.3v 3.3v 0v 3.3v mute1 mute2 0v 3.3v 270pf 50 270pf 13.3nf 12v rfmd ums-1400-a16-g 100pf 5v 0.1f 0.1f loop bandwidth = ~7.6khz 14v 5v 3.3v 100 v tune + ? v vco + gnd gnd gnd gnd gnd vco + vco ? v refo + refo stat cs sclk sdi sdo v d + mute gnd rf ? gnd ltc6945 o_div = 2 rf + v rf + bb ref ? 3.3v 0.1f 51.1 ref + v ref + cp v cp + gnd + 0.01f 100pf 700mhz to 1400mhz 1.0f 22nf lt1678is8 274 4.99k 4.99k 267nf 1f 0.1f 0.1f 47f 1f 3.3v 3.3v spi bus mute2 0.1f 0.01f 180nh 180nh 3.3v 3.3v power combiner 3.3v 100ns 270pf 50 270pf 1 2 s lo out 6945 ta02a lo2 = 350mhz to 700mhz lo1 = 350mhz to 700mhz 13.3nf 12v rfmd ums-1400-a16-g 100pf 5v 0.1f 0.1f loop bandwidth = ~7.6khz 14v 5v 3.3v 100 v tune + ? time (s) ?0.6 lo out power (mhz) mute voltages (v) 3 ?5.0 0 0.4 6945 ta02c 2 1 0 ?0.4 ?0.2 0.2 ?4.5 ?4.0 ?3.5 0.6 mute1 mute2 ltc6945 6945fa for more information www.linear.com/ltc6945
26 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. ltc6945 6945fa for more information www.linear.com/ltc6945
27 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 3/15 changed operating core temperature to operating junction temperature. updated power supply currents. 2 4 ltc6945 6945fa for more information www.linear.com/ltc6945
28 ? linear technology corporation 2011 lt 0315 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc6945 r ela t e d p ar t s typical a pplica t ion ltc6945 wideband point-to-point radio local oscillator v vco + gnd gnd gnd gnd gnd vco + vco ? v refo + refo stat cs sclk sdi sdo v d + mute gnd rf ? gnd ltc6945 o_div = 2 rf + v rf + bb ref ? 3.3v 0.1f 100mhz ref ref + v ref + cp v cp + gnd + 0.01f 100pf 1.0f 18.3nf lt1678is8 113 4.99k 51.1 4.99k 230nf 1f 1f 0.1f 0.1f 47f 3.3v 3.3v spi bus 0.1f 0.01f 68nh 68nh 3.3v 3.3v lo out 4900mhz to 5900mhz in steps of 5mhz 3.3v 100pf 50 100pf 4.7nf 5v rfmd umz-t2-227-o16-g 100pf 6945 ta03a 5v 0.1f 0.1f loop bandwidth = ~21.4khz 11v 5v 3.3v 100 v tune + ? radio local oscillator phase noise, f rf = 5725mhz offset frequency (hz) ?140 phase, noise (dbc/hz) ?130 ?110 ?90 ?80 100 10k 100k 10m 40m 6945 ta03b ?150 1k 1m ?100 ?120 ?160 rms noise = 0.47 rms jitter = 230fs f pfd = 5mhz bw = 21khz part number description comments ltc6946 ultralow noise and spurious integer-n synthesizer with vco 370mhz to 6.4ghz, C226dbc/hz normalized in-band phase noise floor ltc6947 ultralow noise and spurious fractional-n synthesizer 350mhz to 6ghz, C226dbc/hz normalized in-band phase noise floor ltc6948 ultralow noise and spurious frac-n synthesizer with vco 370mhz to 6.4ghz, C226dbc/hz normalized in-band phase noise floor ltc6950 low phase noise and spurious integer-n pll core with five output clock distribution and ezsync 1.4ghz max vco frequency, additive jitter <20fsrms, C226dbc/hz normalized in-band phase noise floor ltc6957 low phase noise, dual output buffer/driver/logic converter optimized conversion of sine waves to logic levels, lvpecl/lvds/ cmos ltc2000 16-/14-/11-bit 2.5gsps dac superior 80dbc sfdr at 70mhz output, 40ma nominal drive and high linearity ltc5569 broadband dual mixer 300mhz to 4ghz, 26.8dbm iip3, 2db gain, 11.7db nf, 600mw power ltc5588-1 ultrahigh oip3 i/q modulator 200mhz to 6ghz, 31dbm oip3, C160.6dbm/hz noise floor lt ? 5575 direct conversion i/q demodulator 800mhz to 2.7ghz, 22.6dbm iip3, 60dbm iip2, 12.7db nf ltc6945 6945fa for more information www.linear.com/ltc6945

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